Optical semiconductor device

ABSTRACT

The present invention includes a first conductor line connected to one end of an optical semiconductor element ( 20 ), and supplying an electric signal to this optical semiconductor element ( 20 ); a second conductor line connected to the other end of the optical semiconductor element ( 20 ), and supplying an electric signal to this optical semiconductor element ( 20 ); a first inductance element ( 21   a ) connected to the one end of the optical semiconductor element ( 20 ), and cutting off the electric signal at a high frequency; and a second inductance element ( 21   b ) connected to the other end of the optical semiconductor element ( 20 ), and cutting off the electric signal at the high frequency, wherein the first and the second conductor lines constitute differential lines.

TECHNICAL FIELD

The present invention relates to an optical semiconductor deviceincluding an optical semiconductor element that outputs an opticalsignal modulated based on an electric signal.

BACKGROUND ART

FIG. 18 is a circuit diagram which illustrates one example of aconventional single-phase feed type optical semiconductor device.Circuits similar to such a circuit are disclosed by, for example,Japanese Patent Application Laid-Open Publication Nos. 9-200150 and8-172401.

In the optical semiconductor device shown in FIG. 18, an LD drivingcircuit 200 that drives a semiconductor laser diode element 310(hereinafter, “LD”) is connected to an LD module 300. A light emissionoutput of the LD 310 is output from an optical fiber 316. Differentialtransistors 202 and 203, which constitute a differential amplifier aredriven by a constant current by a transistor 204, are applied withcomplementary data input signals (a positive phase signal and anantiphase signal), respectively, and output a positive-phase signal. Acollector of the differential transistor 202 is grounded. A collector ofthe differential transistor 203 is connected to one end of a dampingresistor 309, and the other end of the damping resistor 309 is connectedto one electrode (cathode) of the LD 310. The cathode of the LD 310 isconnected to one end of an inductance element 311 having a highimpedance with respect to a high frequency, such as a chip inductance.The other end of the inductance element 311 is connected to a constantcurrent source 314 that supplies a bias current to the LD 310. Theinductance element 311 constitutes a bias circuit for the LD module 300.

FIG. 19 illustrates one example of an eye pattern of electric signalwaveforms output from a circuit such as the LD driving circuit 200 shownin FIG. 18. The LD driving circuit illustrated in this example employs asilicon-germanium semiconductor so as to reduce power consumption of thecircuit.

If this LD driving circuit is driven by a negative voltage as shown inFIG. 18, a first transition of an electric signal pulse corresponding toa first transition of an optical signal pulse is a segment of the eyepattern directed downward whereas a second transition thereof is asegment of the eye pattern directed upward. As shown in FIG. 19, a falltime Tf is longer than a rise time Tr by about 40 percents.

FIG. 20 illustrates one example of an eye pattern of optical signalwaveforms (optical output waveforms) output from the LD module shown inFIG. 18 using the LD driving circuit that outputs electric signalshaving signal waveforms as shown in FIG. 19. This example illustratesthat optical signal waveforms in various patterns are photoelectricallyconverted to electric signals and that the electric signals are overlaidthrough a band filter. In FIG. 20, an upper part is a mark side (lightemission) and the horizontal axis indicates time. FIG. 20 alsoillustrates eye mask regions (regions which are an index todetermination as to whether a signal is deteriorated and in which theeye pattern should not enter).

Eye mask prescription indicated by the eye mask regions are an index tothe performance of the signal waveform. As a gap (an eye mask margin)between the signal waveform (eye pattern) and the eye mask region iswider, better reception sensitivity characteristics can be attained whenan optical receiver receives a signal. In other words, even if anoptical signal is lower in power, error occurs less frequently and goodtransmission characteristics can be ensured.

That is, in order to obtain a signal at a low error rate when theoptical signal output from the optical semiconductor device is receivedand converted to an electric signal and the electric signal isreproduced, it is necessary to prevent the eye pattern from entering theeye mask regions.

Nevertheless, if a modulated signal at 10 Gb/s or more is to betransmitted, the optical output waveform of the LD module isconspicuously deteriorated as shown in FIG. 20. As can be seen from thewaveform shown in FIG. 20, there is an enough margin to the eye maskprescription near an upper left part of a central portion of the eyepattern (a rising part indicated by W1 in FIG. 20). However, the eyemask margin is quite small near an upper right part of the centralportion (a rising part indicated by W2 in FIG. 20), with the resultthere is no margin at all to the eye mask prescription. Therefore, aproblem occurs that if, for example, a surrounding temperature rises, arelaxation oscillation frequency of the optical semiconductor falls andthe signal waveform cannot satisfy the upper right part of the centralportion of the eye mask.

As can be seen, in the conventional optical semiconductor shown in FIG.18, the margin to the eye mask prescription falls as shown in FIG. 20.

A cause for this fall of the eye margin is as follows. If the opticalsemiconductor device is a pulse intensity modulation type opticalsemiconductor device that modulates a light in a wide band from a lowfrequency band to a high frequency band, the fall time of the electricsignal pulse is late as explained above and the eye mask margin that isa margin of the eye pattern falls due to asymmetry of the electricsignal input to the LD module 300. As a result, the transmissioncharacteristics of the optical signal to be output are deteriorated.

FIG. 21 is a frequency response graph if a signal transmission line Pbetween the LD driving circuit 200 and the LD module 300 shown in FIG.18 includes a distributed constant circuit such as a micro-strip lineand if the LD module 300 is viewed from this distributed constantcircuit. FIG. 21 demonstrates that a cutoff frequency (a frequency 3decibels lower from a peak) is about 8.8 gigahertz and that there is asharp decline of the response characteristics at a frequency near 10gigahertz. Reasons for the presence of this sharp decline are asfollows.

In a high frequency region such as a region at the frequency near 10gigahertz, both ends of inductance elements 311 shown in the example ofFIG. 14 are fixed to a ceramic substrate and a plurality of pad sectionseach including a conductor are provided to arrange wirings by wirebonds. Since each pad section functions as a capacitance, a resonance isgenerated by these capacitances, a plurality of wires by the wirebonding that connect the LD 310 to pads provided between the inductanceelement 311 and the matching resistor 309, and a reactance component ofthe inductance element 311 that constitutes the bias circuit. Thisresults in quite sharp damping characteristics.

As can be seen, the conventional optical semiconductor device hasproblems that output characteristics of the optical signal is influencedby poor fall characteristics of the LD driving circuit and thetransmission characteristics of the optical signal is therebydeteriorated.

Further, the conventional optical semiconductor device has a problemthat passing characteristics of the LD module suddenly attenuates at thefrequency near 10 gigahertz. The sharp decline of the characteristicsnear 10 gigahertz particularly causes the great deterioration of theoptical output waveform of the optical semiconductor device. It issignificant to solve this problem.

It is, therefore, an object of the present invention to provide anoptical semiconductor device which improves the deterioration of anoptical output waveform due to the asymmetry between a rise time and afall time of the output waveform of an LD driving circuit and thedeterioration of the optical output waveform such as the deteriorationfollowing a sharp decline of passing characteristics of an opticalsemiconductor module, and which improves the quality of the opticaloutput waveform.

DISCLOSURE OF THE INVENTION

An optical semiconductor device according to the present inventionincludes an optical semiconductor element; a first conductor lineconnected to one electrode of a pair of electrodes of the opticalsemiconductor device, and supplying an electric signal to the opticalsemiconductor element; a second conductor line connected to the otherelectrode of the pair of electrodes of the optical semiconductorelement, and supplying an electric signal to the optical semiconductorelement; a first inductance element connected to the one electrode ofthe optical semiconductor element and the first conductor line; and asecond inductance element connected to the other electrode of theoptical semiconductor element and the second conductor line, wherein thefirst and the second conductor lines constitute a pair of differentiallines.

According to the present invention, the first conductor line and thesecond conductor line can constitute a pair of differential lines, thefirst conductor line connected to one electrode of a pair of electrodeswhich the optical semiconductor device includes can supply an electricsignal to the optical semiconductor element, the second conductor lineconnected to the other electrode of the pair of electrode which theoptical semiconductor element includes can supply an electric signal tothe optical semiconductor element, the first inductance elementconnected to the one electrode of the optical semiconductor element andthe first conductor line can cut off the electric signal at a highfrequency, and the second inductance element connected to the otherelectrode of the optical semiconductor element and the second conductorline can cut off the electric signal at a high frequency.

An optical semiconductor device according to next invention includes anoptical semiconductor element; a first differential input terminalsupplying an electric signal to one of a pair of electrodes of theoptical semiconductor element; a second differential input terminalsupplying an electric signal opposite in phase to the electric signalsupplied by the first differential input terminal, to the otherelectrode of the pair of electrodes of the optical semiconductorelement; a first inductance element connected to the one electrode ofthe optical semiconductor element and the first conductor line, andcutting off the electric signal at a high frequency; and a secondinductance element connected to the other electrode of the opticalsemiconductor element and the second conductor line, and cutting off theelectric signal at a high frequency.

According to the present invention, the first differential inputterminal connected to one of the pair of electrodes which the opticalsemiconductor includes can supply an electric signal to the opticalsemiconductor element, the second differential input terminal connectedto the other electrode of the pair of electrodes which the opticalsemiconductor includes can supply an electric signal to the opticalsemiconductor element, the first inductance element connected to the oneelectrode of the optical semiconductor element can cut off the electricsignal at a high frequency, and the second inductance element connectedto the other electrode of the optical semiconductor element can cut offthe electric signal at the high frequency.

An optical semiconductor device according to next invention includes anoptical semiconductor element; a pair of differential amplifiers eachhaving one terminal and the other terminal connected to one electrodeand the other electrode of a pair of electrodes of the opticalsemiconductor element, respectively, and each supplying an electricsignal to the optical semiconductor element; a first inductance elementconnected to the one electrode of the optical semiconductor element, andcutting off the electric signal at a high frequency; and a secondinductance element connected to the other electrode of the opticalsemiconductor element, and cutting off the electric signal at a highfrequency.

According to the present invention, a pair of differential amplifierseach having one terminal and the other terminal connected to oneelectrode and the other electrode of a pair of electrodes which theoptical semiconductor element includes, respectively, can supplyelectric signals to the optical semiconductor element, the firstinductance element connected to the one electrode of the opticalsemiconductor element can cut off the electric signal at a highfrequency, and the second inductance element connected to the otherelectrode of the optical semiconductor element can cut off the electricsignal at the high frequency.

An optical semiconductor device according to next invention furtherincludes, in addition to the above invention, a pair of matchingresistors connected to the one electrode and the other electrode of theoptical semiconductor element, respectively, and introducing theelectric signals to the optical semiconductor element.

According to the present invention, a pair of resistors connected to theone electrode and the other electrode of the optical semiconductorelement, respectively, can make impedance matching at the high frequencyand efficiently introduce the electric signals to the opticalsemiconductor element.

An optical semiconductor device according to next invention includes, inaddition to the above invention, a first bias circuit including thefirst inductance element and a first resistor connected in parallel tothe first inductance element; and a second bias circuit including thesecond inductance element and a second resistor connected in parallel tothe second inductance element.

According to the present invention, the first bias circuit including thefirst inductance element and the first resistor connected in parallel tothe first inductance element and the second bias circuit including thesecond inductance element and the second resistor connected in parallelto the second inductance element can prevent a resonance caused byreactance components of the inductance elements, inductances of wirebonds, capacities of pads, and parasitic capacitances of the inductanceelements, and cut off electric signals at high frequencies in widefrequency bands.

An optical semiconductor device according to next invention includes, inaddition to the above invention, a filter that cuts off frequencieshigher than at least a maximum repetition frequency of a digital signal,the filter provided between the first and the second conductor lines andthe pair of matching resistors.

I According to the present invention, the filter provided between thefirst and the second conductor lines and the pair of matching resistorscan cut off frequencies higher than at least the maximum repetitionfrequency of the digital signal, and remove a ringing of electric inputwaveforms in unnecessary frequency bands.

In an optical semiconductor device according to next invention, thefilter includes a first conductor finger section and a second conductorfinger section in which a plurality of conductors crossing the first andthe second conductor lines are formed, respectively, to have a combshape, the first conductor finger section and the second conductorfinger sections being alternately arranged.

According to the present invention, the filter which includes the firstconductor finger section and the second conductor finger section inwhich a plurality of conductors crossing the first and the secondconductor lines are formed, respectively, to have a comb shape, and inwhich filter the first conductor finger section and the second conductorfinger sections are alternately arranged, can cut off frequencies higherthan at least the maximum repetition frequency of the digital signal andremove the ringing of electric input waveforms in unnecessary frequencybands.

An optical semiconductor device according to next invention includes, inaddition to the above invention, a package containing therein the firstand the second conductor lines; a lens that condenses a light emittedfrom the optical semiconductor element; and an optical fiber holdingmember that holds an optical fiber.

According to the present invention, a semiconductor optical modulationdevice including the package containing therein the first and the secondconductor lines, the lens that condenses the light emitted from theoptical semiconductor element, and the optical fiber holding member thatholds the optical fiber can be constituted.

In an optical semiconductor device according to next invention, thefirst and the second inductance elements are air-cored coils.

According to the present invention, the first and the second air-coredcoils enable making the bias circuits for cutting off high frequencyelectric signals in wide frequency bands small in size.

In an optical semiconductor device according to next invention, theoptical semiconductor element is a semiconductor laser diode.

According to the present invention, the semiconductor optical modulationdevice that reduces the deterioration of the optical output waveforms ofthe semiconductor laser diode can be constituted.

The first and the second inductance elements may supply bias currents.

An optical semiconductor device according to next invention includes anoptical semiconductor element; first and second conductor linesconnected to a pair of electrodes of the optical semiconductor element,and supplying differential signals to the optical semiconductor element,respectively; a first terminal electrically connected to the firstconductor line and one electrode of the pair of electrodes of theoptical semiconductor element; and a second terminal electricallyconnected to the second conductor line and the other electrode of theoptical semiconductor element, wherein the first and the secondterminals are connected to bias circuits that cut off high frequencies,respectively.

According to the present invention, the first and the second conductorlines connected to a pair of electrodes of the optical semiconductorelement supply differential signals to the optical semiconductorelement, respectively, and the first terminal electrically connected tothe first conductor line and one electrode of the pair of electrodes ofthe optical semiconductor element and the second terminal electricallyconnected to the second conductor line and the other electrode of theoptical semiconductor element are connected to the bias circuits thatcut off high frequencies, respectively. It is thereby possible toprevent the resonance caused by the reactance components of theinductance elements, the inductances of the wire bonds, and thecapacities of the pads, and cut off high frequency electric signals inwide frequency bands.

An optical semiconductor device according to next invention includes anoptical semiconductor element; a first conductor line having one endconnected to one of a pair of electrodes of the optical semiconductorelement, and supplying an electric signal to the optical semiconductorelement; a second conductor line having one end connected to the otherelectrode of the pair of electrodes of the optical semiconductorelement, and supplying an electric signal to the optical semiconductorelement; a first inductance element connected to the one electrode ofthe optical semiconductor element and the first conductor line; and asecond inductance element connected to the other electrode of theoptical semiconductor element and the second conductor line, wherein theoptical semiconductor element is driven by a push-pull operation.

According to the present invention, the first conductor line connectedto one of a pair of electrodes of the optical semiconductor elementdriven by the push-pull operation can supply an electric signal to theoptical semiconductor element, the second conductor line connected tothe other electrode of the pair of electrodes of the opticalsemiconductor element can supply an electric signal to the opticalsemiconductor element, the first inductance element connected to one endof the optical semiconductor element can cut off high frequency electricsignals, and the second inductance element connected to the other end ofthe optical semiconductor element can cut off high frequency electricsignals.

In an optical semiconductor device according to next invention,impedances of at least two bias circuits are set asymmetric.

According to the present invention, at least two bias circuits havingasymmetric impedances can constitute the semiconductor opticalmodulation device which improves a waviness of frequency responsecharacteristics.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit block diagram which illustrates one example of anoptical semiconductor device according to the first embodiment;

FIG. 2(a) is an explanatory view which typically illustrate risecharacteristics and fall characteristics of a pair of differentialtransistors in an LD driving circuit;

FIG. 2(b) is an explanatory view which illustrates a principle that therise characteristics and the fall characteristics of the pair ofdifferential transistors are averaged;

FIG. 3 illustrates that optical signal waveforms in various patterns arephotoelectrically converted to electric signals, the electric signalsare passed through a band filter, and that the electric signals areoverlaid;

FIG. 4(a) is a graph which illustrates frequency responsecharacteristics when the LD module shown in FIG. 1 is viewed from adistributed constant circuit;

FIG. 4(b) is a graph which illustrates frequency responsecharacteristics when respective bias circuits are set to have differentimpedances;

FIG. 5 is a circuit block diagram which illustrates one example of theoptical semiconductor device according to the second embodiment;

FIG. 6(a) is a top view of a filter;

FIG. 6(b) is an illustration of this filter viewed from an arrow Pdirection;

FIG. 7 is a graph which compares frequency characteristics before andafter the filter is inserted;

FIG. 8 is an equivalent circuit diagram which simulates a high frequencyoperation of the optical semiconductor device shown in FIG. 5;

FIG. 9(a) is a simplified equivalent circuit diagram which simulates ahigh frequency operation of a conventional semiconductor device shown inFIG. 18;

FIG. 9(b) is a graph which illustrates a simulation result of thefrequency response characteristics of this equivalent circuit;

FIG. 10(a) is a simplified equivalent circuit diagram which simulatesthe high frequency operation of the optical semiconductor device(differential lines) according to the present invention shown in FIG. 1;

FIG. 10(b) is a graph which illustrates a simulation result of thefrequency response characteristics of this equivalent circuit;

FIG. 11(a) is a circuit block diagram which illustrates theconfiguration of a bias circuit in the equivalent circuit shown in FIG.10(a) in detail;

FIG. 11(b) is a graph which illustrates the simulation result of thefrequency response characteristics based on circuit conditions shown inFIG. 11(a);

FIG. 11(c) is a circuit block diagram which illustrates theconfiguration of the bias circuit in the equivalent circuit shown inFIG. 9(a) in detail;

FIG. 11(d) is a graph which illustrates the simulation result of thefrequency response characteristics based on the circuit conditions;

FIG. 12(a) is a circuit block diagram which illustrates an identicalequivalent circuit to that shown in FIG. 11(a);

FIG. 12(b) is a graph which illustrates the simulation result based oncircuit conditions shown in FIG. 12(a);

FIG. 12(c) is a graph which illustrates the simulation result offrequency response characteristics in the equivalent circuit shown inFIG. 11(a) when an inductance L4 of a wire bond 23 a (or 23 b) ischanged from 3 nanohenries to 1 nanohenry;

FIG. 13(a) illustrates an identical equivalent circuit to that shown inFIG. 11(a);

FIG. 13(b) is a graph which illustrates a simulation result based oncircuit conditions shown in FIG. 13(a);

FIG. 13(c) is a graph which illustrates the simulation result of thefrequency response characteristics when an inductance L1 of aninductance element is changed in the equivalent circuit shown in FIG.11(a);

FIG. 14 illustrates the outside configuration of the LD module whichincludes a can package and a receptacle;

FIG. 15(a) is a horizontal sectional view (a view of a surface parallelto x shown in FIG. 14) of the LD module;

FIG. 15(b) is a vertical sectional view (a view of a surface parallel toy shown in FIG. 14) of the LD module;

FIG. 16 is a perspective view which illustrates the can package in astate in which a cap is detached;

FIG. 17(a) is a top view in a state in which an upper cap is detached;

FIG. 17(b) is a cross-sectional view taken along a line II of FIG. 17(a)in a state in which the upper cap is attached;

FIG. 18 is a circuit diagram which illustrates one example of aconventional single-phase feed type optical semiconductor device;

FIG. 19 illustrates one example of an eye pattern of electric signalwaveforms output from a circuit such as an LD driving circuit shown inFIG. 18;

FIG. 20 illustrates one example of an eye pattern of optical signalwaveforms (optical output waveforms) output from the LD module shown inFIG. 18; and

FIG. 21 is a graph which illustrates the frequency responsecharacteristics when a signal transmission path P between the LD drivingcircuit and the LD module shown in FIG. 18 is constituted by adistributed constant circuit such as a micro-strip line and when the LDmodule is viewed from this distributed constant circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Exemplary embodiments of the optical semiconductor device according tothe present invention is described in detail below with reference to theaccompanying drawings.

FIRST EMBODIMENT

FIG. 1 is a circuit block diagram which illustrates one example of anoptical semiconductor device according to the first embodiment. In FIG.1, an LD driving circuit 1 includes an input buffer 11 which has adifferential input configuration, a pair of differential transistors 12and 13 which have differential configuration and which output anantiphase signal and a positive phase signal, respectively, a transistor14 which performs a constant-current operation, and resistors 15 and 16which are loads of collectors of the differential transistors 12 and 13,respectively, and which make impedance matching.

The input buffer 11 shapes waveforms of input antiphase signal andpositive phase signal, and generates the adjusted antiphase signal andpositive phase signal to be input to bases of the differentialtransistors 12 and 13.

The paired differential transistors 12 and 13 that have the differentialconfiguration and the transistor 14 constitute a differential amplifier.Collector sides of the differential transistors 12 and 13 are connectedto one side of the resistors 15 and that of the resistor 16,respectively. The other sides of the resistors 15 and 16 are connectedto ground terminals, respectively. Emitters of the differentialtransistors 12 and 13 are connected to the transistor 14 which performsthe constant-current operation. An antiphase signal output terminal ofthe input buffer 11 is connected to the base of the differentialtransistor 12, and a positive phase signal output terminal of the inputbuffer 11 is connected to the base of the differential transistor 13. Anemitter side of the transistor 14 and a voltage input terminal of theinput buffer 11 are both connected to a negative power supply (Vee).

Collector-side output terminals of the differential transistors 12 and13 are connected to a pair of electrodes (an anode and a cathode) of anLD 20 through a distributed constant circuit 18, which includesmicro-strip lines or grounded coplanar lines, and matching resistors 19a and 19 b, respectively.

The differential transistors 12 and 13 may be replaced by field-effecttransistors (hereinafter, “FETs”). If the FETs are employed, the anodeand cathode of the LD 20 are connected to drains of the FETs,respectively.

LD module 2 sides of the differential transistors 12 and 13 areconnected to the LD 20 having a high frequency impedance of about 5 ohmsthrough the distributed constant circuit 18 and the matching resistors19 a and 19 b for impedance matching each having an impedance of about20 ohms. The anode side of the LD 20 is bonded to a conductor lineelectrically connected to the matching resistor 19 b by soldering or thelike, and the cathode side of the LD 20 is connected to a conductor lineelectrically connected to the matching resistor 19 a. The distributedconstant circuit 18 is constituted so that the output terminals of thedifferential transistors 13 and 12 of differential type in the LDdriving circuit 1 are connected to the matching resistors 19 a and 19 bby differential lines or wire bonds, respectively. The differentiallines are obtained by arranging two conductor lines to be proximate toeach other, and signal transmission is performed so that one of inputsignals to the two conductor lines is a positive-phase signal and theother input signal is an antiphase signal. It is thereby possible toimprove electrical coupling between the two conductor lines and reduceleakage loss of an electric field.

In, for example, the conventional single-phase driving type opticalsemiconductor device, since a high current that drives the LD is fedback to the LD driving circuit through a ground, a ground potentialchanges. This ground potential change often adversely affects an opticalreception electronic circuit arranged proximate to the device anddetecting a feeble current. In this embodiment, by contrast, the opticalsemiconductor device performs a push-pull operation with respect to theLD using the differential lines. Therefore, the optical semiconductordevice in this embodiment has advantages in that the high currentcarries across the differential lines, the ground potential has lesschange, and peripheral circuits are less influenced.

The differential lines include differential type micro-strip lines(micro-strip differential lines) obtained by arranging two signaltransmission lines proximate to each other, differential type groundedcoplanar lines (grounded coplanar differential lines), differential pins(or leads) obtained by arranging two conductor pins proximate to eachother, or the like.

A solenoid 21 a having a high impedance with respect to a high frequencyand a resistor 22 a connected in parallel to this solenoid 21 a andreducing a Q value for preventing a resonance constitute a first biascircuit 28 a. A solenoid 21 b having a high impedance with respect tothe high frequency and a resistor 22 b connected in parallel to thissolenoid 21 b and reducing the Q value for preventing the resonanceconstitute a second bias circuit 28 b. Air-cored coils which cause biascurrents (direct currents) to pass through, and which suppress modulatedsignals (electric signals at several hundred kilohertz to several tensof gigahertz) output from the LD driving circuit 1 from leaking from thefirst and the second bias circuits 28 a and 28 b, i.e., which cut offhigh frequency signals are used for the solenoids 21 a and 21 b,respectively. The solenoid 21 a in the first bias circuit 28 a and thesolenoid 21 b in the second bias circuit 28 b are connected to theconductor lines, one ends of which are electrically connected to theanode and cathode of the LD 20, through the wire bonds 23 a and 23 b,respectively. Thus, the bias circuit 28 a is connected to the conductorline electrically connected to the matching resistor 19 a through thewire bond 23 a, and connected to the cathode of the LD 20 through a wirebond 29. The bias circuit 28 b is connected to the conductor lineelectrically connected to the matching resistor 19 b through the wirebond 23 b, and connected to the soldered conductor line (pad) on theanode of the LD 20.

The anode side of the LD 20 is connected to a ground terminal throughthe parallel circuit in the second bias circuit 28 b. The cathode sideof the LD 20 is connected to a constant current source 24 through theparallel circuit in the second bias circuit 28 a. The constant currentsource 24 includes a transistor and an emitter side of the constantcurrent source 24 is connected to a negative power supply (Vee). Thisnegative power supply is set equal in voltage to the negative powersupply (Vee) to which the transistor 14 in the LD driving circuit 1 isconnected. Alternatively, they may be set at different voltages.

The bias circuits 28 a and 28 b, together with the wire bonds 23 a and23 b and the like, act as ungrounded open terminals for highfrequencies.

With the driving configuration of this LD 20, direct current(hereinafter, “DC”) bias currents are supplied to the anode and cathodeof the LD 20 through the paired first and second bias circuits 28 a and28 b, respectively, and high frequency modulation currents are input tothe anode and cathode of the LD 20 in a differential manner by thepaired differential transistors 12 and 13 of the differential type,respectively.

Namely, if a state of the differential transistor 12 in the LD drivingcircuit 1 changes from ON to OFF (a state of the differential transistor13 changes from OFF to ON), the modulation current flows in the LD 20and a state of an laser light output from the LD 20 changes from OFF toON. If the state of the differential transistor 13 changes from ON toOFF (the state of the differential transistor 12 changes from OFF toON), the modulation current flowing in the LD 20 decreases and the stateof a laser light output of the LD 20 changes from ON to OFF.

Accordingly, the modulated electrical signals output from thedifferential transistors 12 and 13 constituted to be differential fromeach other in the LD driving circuit 1 are transmitted to the LD 20through the distributed constant circuit 18 and the like, and convertedto optical modulation signal in the LD 20. The modulated optical signalsgenerated from the LD 20 are condensed on an optical fiber 26 by acondenser lens 25 and the condensed, modulated optical signal is outputthrough this optical fiber 26.

FIG. 2(a) is an explanatory view which typically illustrates rising andfall characteristics of the paired differential transistors 12 and 13 inthe LD driving circuit 1. FIG. 2(b) is an explanatory view whichillustrates a principle that the rising and fall characteristics of thepaired differential transistors 12 and 13 are averaged.

As shown in FIG. 2(a), if a rise time of the differential transistor 12or 13 (it is assumed that the transistors 12 and 13 are equivalent incharacteristics) is tr and a fall time thereof is tf, tr and tfsatisfies a relationship of tr<tf. This is already explained above.

Further, as explained, the positive-phase signal and the antiphasesignal are passed through the distributed constant circuit 18, and oneis connected to the cathode of the LD 20 through the matching resistor19 a and the other is connected to the anode of the LD 20 through thematching resistor 19 b. By so connecting, when the differentialtransistor 12 rises, the differential transistor 13 simultaneously risesand when the differential transistor 12 falls, the differentialtransistor 1 3 simultaneously falls. Therefore, if the operation isviewed from the LD 20, the LD 20 is push-pull driven by the paireddifferential transistors 12 and 13.

As for the circuits in the conventional optical semiconductor deviceshown in FIG. 18, in the LD driving circuit 200, the paired transistorsperform a differential operation. If the operation is viewed from the LD310, the operation is simply such that when the differential transistor203 rises, a current flows in the LD 310, and that when the differentialtransistor 203 falls, no current flows in the LD 310. Namely, if theoperation is viewed from the LD 310 (or the distributed constant circuitthat connects the LD driving circuit 200 to the LD 310), the LD 310 isnot push-pull driven.

The circuits in the optical semiconductor device according to thepresent invention shown in FIG. 1 perform such an push-pull operation.Therefore, the distributed constant circuit 18 serves as differentiallines, performs current push and pull for the LD 20 simultaneously. Ifthe operation is viewed from the LD 20, the circuits operate for anaverage time ((tr+tf)/2) between the rise time (tr) of the differentialtransistor 12 and the fall time (tf) of the differential transistor 13.As a result, as shown in FIG. 2(b), the paired transistors 12 and 13exhibit symmetric rise characteristics that the rise time and the falltime are averaged.

FIG. 3 illustrates that optical signal waveforms in various patterns arephotoelectrically converted to electric signals and that the electricsignals are passed through a band filter and overlaid. In FIG. 3, anupper part is a mark side (light emission) and the horizontal axisindicates time. As can be seen from FIG. 3, waveform asymmetry isimproved, there are enough margins to the eye mask prescriptions, andgood transmission characteristics can be obtained, as compared with theeye pattern shown in FIG. 20.

Near an upper right part (a rising part indicated by F in FIG. 3) of acentral portion of the eye pattern, in particular, there is an enoughmargin to the eye mask prescription, so that a margin to a waveformdeterioration following a lowering in the relaxation oscillationfrequency of the LD 20 due to an increase of a using temperature.

Further, in order to the rise characteristics of the LD driving circuithaving the relatively long rise time and fall time shown in FIG. 19, theLD driving circuit 200 is adjusted to have peaking characteristics. Ifso, a slight ringing at a frequency around 15 gigahertz higher than asignal band often occurs and is superposed on the electric waveformshown in FIG. 19.

This ringing can lift up the rising waveform of the optical outputwaveform, a right shoulder (lower right part) of the eye pattern hasmargins to the eye mask, and the quality of the optical output waveformscan be enhanced. If a fundamental wave of a digital signal at 10 Gb/s(minimum pulse) is at, for example, 5 gigahertz, the peaking of the LDdriving circuit 200 is adjusted so that the ringing occurs at aharmonics three times higher than 5 gigahertz, i.e., 15 gigahertz,whereby high-quality optical output waveforms can be obtained.

Japanese Patent Application Laid-Open Publication No. 11-233876discloses an example of the laser module that transmits data withoutjitters by holding a balance between differential load impedances.However, the laser module does not perform a push-pull operation if theoperation is viewed from the LD. Therefore, the invention disclosed bythe publication differs from the present invention.

Japanese Patent Application Laid-Open Publication No. 5-327617 disclosesthat only the fall time is improved by reducing the input impedance ofthe LD which impedance is viewed from the driving circuit. Therefore,the invention of the publication entirely differs in principle from thepresent invention.

FIG. 4(a) is a graph which illustrates frequency responsecharacteristics when the LD module 2 shown in FIG. 1 is viewed from thedistributed constant circuit 18. As explained, the bias circuit 23 a, inwhich the solenoid 21 a and the resistor 22 a are arranged in parallel,is connected to the cathode side of the LD 20 in the LD module 2 shownin FIG. 1, and the bias circuit 23 b, in which the solenoid 21 b and theresistor 22 b are arranged in parallel, is connected to the anode sideof the LD 20 in the LD module 2. Therefore, the respective bias circuits28 a and 28 b generate a resonance due to the capacitance components ofthe pad sections provided on the ceramic substrate or the like,similarly to the example of the conventional LD module 300. However, ifthe LD module 2 is viewed as an equivalent circuit from the distributedconstant circuit 18 side, the two bias circuits appear as if they areconnected in series. Therefore, an amplitude of the resonance can bereduced, and the sharp decline at the frequency around 10 gigahertz asshown in FIG. 21 is prevented. In the example shown in FIG. 4(a), thegraph which illustrates the frequency response characteristics when theimpedances of the resistors 22 a and 22 b are set equal is shown.

FIG. 4(b) is a graph which illustrates the frequency responsecharacteristics when the bias circuits 28 a and 28 b are set to havedifferent impedances. As shown in FIG. 4(b), waviness is improved ascompared with the graph of FIG. 4(a). Specific examples of inductancesand resistors will be explained later in the third and the fourthembodiments.

Japanese Patent Application Laid-Open Publication No. 5-37083 disclosesa problem that an inductance Ls of a bonding wire for connecting a biascircuit to a semiconductor laser and a parasitic capacitance Cs1 of aceramic block of an airtight package provided for connecting the biascircuit to an external circuit cause the deterioration of small signalfrequency characteristics. According to the publication, with a view ofreducing the influence of this parasitic capacitance Cs1, metallizationapplied on a lower surface of a bias line arranged on the ceramic blockof the airtight package is removed and the parasitic capacitance in thecircuit is thereby removed. A lower surface of the ceramic block is apart other than the lower surface of the bias line and metallizationthereof is not removed.

Nevertheless, the invention disclosed by Japanese Patent ApplicationLaid-Open Publication No. 5-37083 employs the single-phase line tosupply a modulated signal to the semiconductor laser. The publicationdoes not disclose an example of the circuit in which differential linesare employed, an example in which two bias circuits are employed, and anexample in which impedances of the two bias circuits are setdifferently. In addition, the invention of the publication differs incircuit configuration from the first embodiment of the present inventionin which the two bias circuits connected to the differential lines arearranged.

Moreover, the invention of Japanese Patent Application Laid-OpenPublication No. 5-37083 moves a damping frequency of 3 decibels of thepassing characteristics caused by the resonance from 2.5 gigahertz to2.9 gigahertz on the frequency axis. The invention of the publicationthus totally differs from the first embodiment of the present inventionin which the amplitude of the resonance is changed.

As can be seen, according to the first embodiment, the opticalsemiconductor element to which the differential lines are connected isdriven by the push-pull operation. Therefore, the first embodimentexhibits advantages in that the asymmetry of the electric drivingwaveform is improved, the quality of the optical output waveform isimproved, and good transmission characteristics can be thereby obtained.

Further, the bias circuits are arranged on the both sides of the opticalsemiconductor element to which the differential lines are connected.Therefore, if the optical semiconductor element is assumed as theequivalent circuit, the two bias circuits appear to be connected inseries to the optical semiconductor element. Hence, the amplitude of theresonance can be reduced, the sharp decline (ripple) of the passingcharacteristics followed by the arrangement of the bias circuits can beimproved, the quality of the optical output waveform can be improved,and the good transmission characteristics can be thereby obtained.

In the first embodiment, the optical semiconductor device in which theLD is directly modulated has been shown. The first embodiment is alsoapplicable to an optical semiconductor device separately including alight source that outputs a light of a certain intensity, such as anoptical semiconductor device using a field absorption type semiconductormodulation element. Such an optical semiconductor device has the samefunctions and advantages as those of the first embodiment.

In the first embodiment, each solenoid is employed as an element thatprevents a serial resonance. However, any other element can be used aslong as the element has an inductance component (the element is aninductance element). For example, a chip inductor including a patternwiring on the ceramic substrate, or a wire having a diameter of 0.01 to0.5 millimeter and a length of about 10 millimeters may be used.

As explained so far, according to the optical semiconductor device inthe first embodiment, the optical semiconductor element to which thedifferential lines are connected is driven by the push-pull operation.Therefore, the optical semiconductor device has advantages in that theasymmetry of the waveform can be improved, the quality of the opticaloutput waveform is improved, and the good transmission characteristicscan be thereby obtained.

Further, according to the optical semiconductor device in the firstembodiment, the bias circuits are arranged on the both sides of theoptical semiconductor element to which the differential lines areconnected. Therefore, the ripple of the passing characteristics followedby the arrangement of the bias circuits can be improved, the quality ofthe optical output waveform can be improved, and the good transmissioncharacteristics can be thereby obtained.

SECOND EMBODIMENT

FIG. 5 is a circuit block diagram which illustrates one example of theoptical semiconductor device in the second embodiment. In FIG. 5, the LDdriving circuit 1 includes the input buffer 11 which has differentialinput configuration, the paired differential transistors 12 and 13 whichhave differential configuration to output an antiphase signal and apositive phase signal, respectively, the transistor 14 which performs aconstant-current operation, and the resistors 15 and 16 which areresistors against the loads of collectors of the differentialtransistors 12 and 13, respectively,,and which make impedance matching.

The input buffer 11 shapes waveforms of input antiphase signal andpositive phase signal, and generates the adjusted antiphase signal andpositive phase signal to be input to bases of the differentialtransistors 12 and 13.

The paired differential transistors 12 and 13 that have the differentialconfiguration and the transistor 14 constitute a differential amplifier.Collector sides of the differential transistors 12 and 13 are connectedto one side of the resistor 15 and that of the resistor 16,respectively. The other sides of the resistors 15 and 16 are connectedto ground terminals, respectively. Emitters of the differentialtransistors 12 and 13 are connected to the transistor 14 which performsthe constant-current operation. The antiphase signal output terminal ofthe input buffer 11 is connected to the base of the differentialtransistor 12, and the positive phase signal output terminal of theinput buffer 11 is connected to the base of the differential transistor13. An emitter side of the transistor 14 and a voltage input terminal ofthe input buffer 11 are both connected to the negative power supply(Vee).

The (collector-side) output terminals of the differential transistors 12and 13 are connected to the anode and the cathode of the LD 20 throughthe distributed constant circuit 18, which includes micro-strip lines orgrounded coplanar lines, and the matching resistors 19 a and 19 b,respectively.

The differential transistors 12 and 13 may be replaced by the FETs. Ifthe FETs are employed, the anode and cathode of the LD 20 are connectedto drains of the FETs, respectively.

The LD module 2 sides of the differential transistors 12 and 13 areconnected to the anode side of LD 20 having a high frequency impedanceof about 5 ohms by soldering and to the cathode side thereof by the wirebond 29 through the distributed constant circuit 18, a filter 27, andthe matching resistors 19 a and 19 b for impedance matching each havingan impedance of about 20 ohms. The differential transistors 12 and 13are connected to the first bias circuit 28 a which includes the solenoid21 a having a high impedance with respect to a high frequency and theresistor 22 a connected in parallel to this solenoid 21 a and reducing aQ value for preventing a resonance, and to the second bias circuit 28 bwhich includes the solenoid 21 b having a high impedance with respect toa high frequency and the resistor 22 b connected in parallel to thissolenoid 21 b and reducing a Q value for preventing a resonance throughwire bonds 23 a and 23 b, respectively.

The anode side of the LD 20 is connected to the ground terminal throughthe wire bond 23 b and the parallel circuit in the second bias circuit28 b. The cathode side of the LD 20 is connected to the biasconstant-current source 24 through the wire bonds 29 and 23 a and theparallel circuit in the second bias circuit 28 a. The constant-currentsource 24 includes a transistor and an emitter side of the constantcurrent source 24 is connected to the negative voltage source (Vee).This negative voltage source is equal in voltage to the negative voltagesource (Vee) to which the transistor. 14 in the LD driving circuit 1 isconnected. Alternatively, these negative voltage sources may be set atdifferent voltages.

Similarly to the first embodiment, DC bias currents are supplied to theanode and cathode of the LD 20 through the paired bias circuits 28 a and28 b, and high frequency modulated signals are input to the anode andcathode of the LD 20 by the paired differential type differentialtransistors 12 and 13 in a differential manner.

If a peaking is applied to the LD driving circuit 1 by changing acircuit constant, not shown in FIG. 5, in order to improve the risecharacteristics of the differential transistors 12 and 13 in the LDdriving circuit 1, a ringing at cycles of about 15 gigahertz occurs. Thefilter 27 shown in FIG. 5 is a lowpass filter for removing this ringing.

In a 1.31 micrometer wavelength band in which optical fiber dispersionis less influential, waveform change after optical fiber transmission issmall and this ringing waveform is attenuated by a filter of a receiver.Therefore, an optical output waveform having larger margins to the eyemask can be obtained. This ringing can be, therefore, actively utilizedfor the improvement of the signal waveform after the signal is passedthrough the filter of the receiver. However, in a 1.55 micrometerwavelength band in which the optical fiber dispersion influence islarge, if this ringing waveform is present, a wavelength chirp resultingfrom the optical semiconductor light emitting element grows and thechirp may possibly adversely affect the waveform after the signal istransmitted over the optical fiber. For this reason, the ringing isremoved by the filter 27.

FIG. 6(a) is a top view of the filter 27, and FIG. 6(b) is anillustration of this filter 27 viewed from an arrow P direction. In FIG.6(a) and FIG. 6(b), the filter 27 includes a pair of micro-stripdifferential lines 39 on an upper surface of a ceramic substrate 41 anda ground. conductor 40 on a lower surface thereof. In addition, acomb-like strip conductor electrode 38 is formed alternately from thepaired micro-strip conductor lines 39 in an inward direction orthogonalto the micro-strip conductor lines 39.

FIG. 7 is a graph which compares frequency response characteristicsbefore and after insertion of the filter 27. In FIG. 7, C1 indicates thecurve of FIG. 4(b) and indicates a waveform in which the waviness of theresponse characteristics is improved by setting the impedances of thebias circuits 28 a and 28 b shown in FIG. 5 asymmetric to each other. C2is a waveform indicating the response characteristics if the peaking isapplied to the LD driving circuit 1 shown in FIG. 5 by changing thecircuit constant, not shown when a ringing at cycles of about 15gigahertz occurs. C3 is a waveform which indicates the responsecharacteristics when the ringing around 15 gigahertz is cut off by thefilter 27. FIG. 7 shows that flat and good frequency responsecharacteristics are obtained up to the frequency exceeding 12 gigahertz.

Japanese Patent Application Laid-Open Publication No. 7-38185 discloses,in FIG. 6, a circuit in which serial circuits including a capacitanceand a resistor are inserted in parallel to an LD element and whichthereby prevents the ringing of rise characteristics. An object of thiscircuit is, however, to remove an overshoot which occurs because no biascurrent is applied and a relaxation oscillation, which object differsfrom the object of the present invention. Further, the circuit of thepublication differs from the present invention in that the circuit is asingle-phase feed type and also differs in circuit configuration.

Japanese Patent Application Laid-Open Publication No. 7-46194 discloses,in FIG. 1 and FIG. 2, a circuit which changes a matching state byconnecting, in parallel, serial circuits including an inductance and aresistor to an LD element between a matching resistor and an LD drivingcircuit, to thereby prevent a ringing. However, the invention differsfrom the present invention in object and circuit configuration and alsodiffers in that the circuit is of a single-phase feed type.

FIG. 8 is a simplified equivalent circuit diagram which simulates a highfrequency operation of the optical semiconductor device shown in FIG. 5.Reference symbol 31 denotes an output impedance of the LD drivingcircuit. On an LD module side, reference symbols correspond to thosethat denote the respective element of the LD module shown in FIG. 5,i.e., reference symbols 19 a and 19 b denote the matching resistors, 20denotes an LD, and 27 denotes the filter.

If it is assumed herein that resistances of the matching resistors 19 aand 19 b are Rd, an internal resistance of the LD 20 is r, a capacitanceof the filter 27 is C, and the output impedance of the LD drivingcircuit is Z, then an approximate equation of a cutoff frequency fc ofthis equivalent circuit is expressed as follows:${{fc} = \frac{1}{2\quad\pi\quad{RC}}},{{{where}\quad R} = \frac{\left( {{2{Rd}} + r} \right)Z}{{2{Rd}} + r + Z}}$

For example, if the impedance Z of the LD driving circuit side is 100ohms, the internal resistance r of the LD 20 is 8 ohms, and theresistances Rd of the matching resistors are 45 ohms, and thecapacitance C of the filter 27 is 0.16 picofarad, then the cutofffrequency fc is approximated to about 10 gigahertz. Since the actualcircuit constant is complicated, the cutoff frequency cannot be simplyobtained. However, if the capacitance is set based on this cutofffrequency fc, a desired filter effect can be obtained.

As explained, according to the second embodiment, the opticalsemiconductor device includes the first and the second conductor fingersections in which a plurality of conductors crossing the first and thesecond conductor lines, respectively, are formed into a comb, the filterin which the first conductor finger section and the second conductorfinger section are alternately arranged cuts off frequencies at leasthigher than a maximum repetition frequency, and the filter removes orreduces the unnecessary ringing of the LD output which occurs when thepeaking is applied to the LD driving circuit. Therefore, it is possibleto improve a signal-to-noise ratio of the optical output signal, toimprove the quality of the optical output waveform, accordingly, andobtain the good transmission characteristics.

In the second embodiment, the example of using the comb-like filter asthe element that prevents the ringing is shown. Any other element can beused as long as the element has a capacitance component and the elementcan be constituted by an ordinary conductor pattern or the like.

In the second embodiment, the optical semiconductor device in which theLD is directly modulated is illustrated. The second embodiment is alsoapplicable to an optical semiconductor device separately including alight source that outputs a light of a certain intensity, such as anoptical semiconductor device using a field absorption type semiconductormodulation element. Such an optical semiconductor device has the samefunctions and advantages as those of the second embodiment.

THIRD EMBODIMENT

In the first embodiment, the advantages of using the differential lineshave been explained while centering around the advantage of compensatingthe asymmetry of the rise/fall characteristics of the LD driving circuitand improving the optical output waveform. By employing the differentiallines, there is an advantage in that frequency characteristics can beimproved besides the advantage of compensating the asymmetry of the riseand fall characteristics. In this embodiment, the advantage of improvingthe frequency characteristics will be explained while referring toequivalent circuits for specific examples of reactances and resistances.

FIG. 9(a) is a simplified equivalent circuit diagram which simulates ahigh frequency operation of the conventional optical semiconductordevice shown in FIG. 18. In FIG. 9(a), reference symbol 31 denotes theoutput impedance of the LD driving circuit, 309 denotes a matchingresistor, and 310 denotes the internal resistance of the LD. Referencesymbol 329 is the wire bond that connects pads, not shown in FIG. 9(a),provided on the conductor line electrically connected to the matchingresistor 309 to the cathode of the LD 310. Reference symbol 32 denotesthe bias circuit including the inductance element 311 such as thesolenoid. Although the resistances should actually be reactances, theresistances are shown for simplifying explanation of fundamental passingcharacteristics in FIG. 9 and FIG. 10.

FIG. 9(b) is a graph which illustrates a simulation result of thefrequency response characteristics of this equivalent circuit. FIG. 9(b)illustrates the simulation result when the output impedance Z1 of the LDdriving circuit side is 50 ohms, the internal resistance r1 of the LD310 is 8 ohms, the resistance R3 of the matching resistor 309 is 40ohms, the inductance L of the wire bond 329 is 0.5 nanohenries, and theimpedance of the bias circuit 32 is 50 ohms. FIG. 9(b) demonstrates thata 3-decibel band (between m1 and m2 where the frequency is lower by 3decibels than that of m1) is at about 10.6 gigahertz.

FIG. 10(a) is a simplified equivalent circuit diagram which simulatesthe high frequency operation of the optical semiconductor device(differential lines) according to the present invention shown in FIG. 1.In FIG. 10(a), reference symbol 31 denotes the output impedance of theLD driving circuit, 19 a and 19 b denote the matching resistors, 20denotes the LD, 29 denotes the wire bond, and 32 and 33 denote therespective bias circuits.

FIG. 10(b) is a graph which illustrates a simulation result of thefrequency response characteristics of this equivalent circuit. FIG.10(b) illustrates the simulation result when the output impedance Z1 ofthe LD driving circuit side is 100 ohms, the internal resistance r1 ofthe LD 20 is 8 ohms, the resistances R3 of the matching resistors 19 aand 19 b are 40 ohms, the inductance L of the wire bond 29 is 0.5nanohenry, and the impedances of the bias circuits 32 and 33 are 50ohms. FIG. 10(b) demonstrates that a 3-decibel band (between m3 and m4where the frequency is lower by 3 decibels than that of m3) is at about18.6 gigahertz.

The substrate side (anode) of the LD element is fixed to a feed line bysoldering or the like. Therefore, the inductance component on the LDmodule side is mainly caused by the wire bond on the cathode side of theLD element, and there is hardly a difference in impedance componentbetween the differential feed circuit and the singe-phase feed circuit.On the other hand, the circuit that employs the differential lines ofthe impedance viewed from the LD element side is about twice as high asthat of the single-phase feed circuit. As a result, by using thedifferential lines, the frequency characteristics (passingcharacteristics) are improved.

As can be understood, by connecting the LD driving circuit to the LDmodule using the differential lines, the frequency characteristics canbe improved.

FOURTH EMBODIMENT

FIG. 11(a) is a circuit diagram which illustrates the configuration ofthe bias circuits In the equivalent circuit shown in FIG. 1 0(a) indetail. Since the configuration and operation of this equivalent circuitare the same as those explained in the first embodiment, they will notbe explained herein. In this fourth embodiment, the characteristics ofthe equivalent circuit in the first embodiment will be explained whilereferring to specific examples of inductances, capacitances, andresistances.

FIRST SPECIFIC EXAMPLE

Pieces of data on the respective elements of the equivalent circuit ofthe optical semiconductor device in the first specific example are asfollows if using symbols shown in FIG. 11(a). Resistances R1 and R2 ofthe resistors 22 a and 22 b are 1,000 ohms, resistances R3 and R4 of thematching resistors 19 a and 19 b are 40 ohms, inductances L1 and L2 ofthe solenoids 21 a and 21 b are 0.5 nanohenry, inductances L4 and L5 ofthe wire bonds 23 a and 23 b are 3 nanohenries, the resistance Z1 of theLD driving circuit side is 100 ohms, the resistance r1 of the LD 20 is 8ohms, and parasitic capacitances C1, C2, C3, and C4 of the bias circuitsare 0.1 picofarad. FIG. 11(b) is a graph which illustrates a simulationresult of the frequency characteristics based on these circuitconditions.

FIG. 11(c) is a circuit block diagram which illustrates theconfiguration of the bias circuits in the equivalent circuit shown inFIG. 9(a) in detail. Since the configuration and operation of thisequivalent circuit are the same as those explained in the conventionalart, they will not be explained herein. Pieces of data on the respectiveelements of the equivalent circuit are as follows if using symbols shownin FIG. 11(c). R2 is 1,000 ohms, R3 is 40 ohms, the inductance L2 of theinductance element 311 is 100 nanohenries, L3=0.5 nanohenry, L5=3nanohenries, and the parasitic capacitances C2 and C4 of the biascircuits are 0.1 picofarad. FIG. 11(d) is a graph which illustrates asimulation result of the frequency characteristics based on thesecircuit conditions.

As shown in the simulation results of FIG. 11(b) and FIG. 11(d), if theoptical semiconductor device employs the differential feed type biascircuits, the amplitude of the resonance ripple caused by the biascircuits can be reduced, as compared with the device that employs thesingle-phase feed type bias circuits. The result of FIG. 11(b)corresponds to that of FIG. 4(a) which illustrates the experimentalresult of the differential feed type optical semiconductor device in thefirst embodiment, and that of FIG. 11(d) corresponds to that of FIG. 21which illustrates the experimental result of the single-phase feed typeoptical semiconductor device. It is noted, however, that theexperimental results of FIG. 4(a) and FIG. 21 include the frequencycharacteristics of the LD driving circuits 1 and 200 and a highfrequency region is cut off.

Japanese Patent Application Laid-Open Publication No. 5-37083 disclosesthe circuit in which a ground surface of a feed-through of the packageis removed so as to reduce parasitic capacitances outside of the wallsurface of the package of the optical module with a view of improvingthe resonance ripple which occurs due to the capacitances of the biascircuit. This circuit, however, employs a single-phase line and differsin circuit configuration from that of the present invention.

SECOND SPECIFIC EXAMPLE

The characteristics of the bias circuits if different conditions are setfor the equivalent circuit of the optical semiconductor device in thefirst embodiment, will be explained as the second specific example ofthe inductances, capacitances, and resistances.

FIG. 12(a) is a circuit block diagram which illustrates the identicalequivalent circuit to that shown in FIG. 11(a). FIG. 12(b) is a graphwhich illustrates a simulation result based on circuit conditions shownin FIG. 12(a), and corresponds to the graph shown in FIG. 11(b). FIG.12(c) is a graph which illustrates a simulation result of the frequencyresponse characteristics when the inductance L4 of the wire bond 23 a(or 23 c) is changed from 3 nanohenries to 1 nanohenry.

As shown in the simulation results of FIG. 12(b) and FIG. 12(c), bymaking the inductance components of the wire bond connecting the biascircuit to the LD element and the like asymmetric vertically, afrequency at which the resonance ripple occurs can be set high. Althoughthe amplitude of the ripple increases, a region in which the rippleoccurs can be forced out of the band. Therefore, this is advantageouswhen a desired band is to be secured.

THIRD SPECIFIC EXAMPLE

The characteristics of the bias circuits if different conditions are setfor the equivalent circuit of the optical semiconductor device in thefirst embodiment, will be explained as the third specific example ofinductances, capacitances, and resistances.

FIG. 13(a) is a circuit block diagram which illustrates the identicalequivalent circuit to that shown in FIG. 11 (a). FIG. 13(b) is a graphwhich illustrates a simulation result based on circuit conditions shownin FIG. 13(a), and corresponds to the graph shown in FIG. 11(b). FIG.13(c) is a graph which illustrates a simulation result of the frequencyresponse characteristics when the inductance L1 of the solenoid 21 a ischanged in the equivalent circuit of FIG. 11(a). As regards the solenoid21 a and the resistance 22 a, FIG. 13(b) is the graph before theinductance L1 is changed while setting L1=100 nanohenries and R1=1,000ohms, and FIG. 13(c) is the graph after the inductance L1 is changedwhile setting L1=10 nanohenries and R1=400 ohms.

As shown in the simulation results of FIG. 13(b) and FIG. 13(c), bymaking the impedances of the solenoid 21 a (or 21 b) and the resistor 22a (or 22 b) connected in parallel to each other in the bias circuitasymmetric vertically, the amplitude of the resonance ripple can befurther reduced. This is the same in content as that shown in theexperimental result of FIG. 4(b) which illustrates the first embodiment.In the experimental result of FIG. 4(b) which illustrates the firstembodiment, the frequency characteristics of the LD driving circuit 1are included and the high frequency region is cut off.

As can be seen, according to the fourth embodiment, by connecting the LDdriving circuit to the LD module using the differential lines, theamplitude of the resonance ripple can be reduced. In addition, by makingthe inductance components of the wire bonds connecting the bias circuitsto the LD element and the like asymmetric vertically by changing thelengths of the wire bonds and the like, the frequency at which theresonance ripple occurs can be set high. Further, by making theimpedances of the inductance element and the resistance connected inparallel to each other in the bias circuit asymmetric vertically, theamplitude of the resonance ripple can be further reduced.

FIFTH EMBODIMENT

An optical semiconductor element module in the fifth embodiment of thepresent invention will first be explained with reference to FIG. 14 toFIG. 16.

FIG. 14 illustrates the outside configuration of the opticalsemiconductor element module (hereinafter, “LD module” since an exampleof mounting the LD will be mainly explained in this fifth embodiment)103 which includes a can package 101 and a receptacle 102. FIG. 15(a)and FIG. 15(b) are a horizontal sectional view (a view of a surfaceparallel to x shown in FIG. 14) and a vertical sectional view (a view ofa surface parallel to y shown in FIG. 14) of the LD module 103,respectively.

As shown in FIG. 14 and FIG. 15, the can package 101 includes adisk-like stem 110 on which bias feed pins ( 144 a, 144 b), highfrequency signal pins ( 141 a, 141 b), and the like are mounted, atrapezoidal pedestal 111 (a pedestal block) on which a plurality ofceramic substrates are mounted, the condenser lens 25 which condenses alaser light emitted from the LD 20, a cylindrical cap 113 which airtightseals the pedestal 111 and the like from the outside, and the like.

As shown in FIG. 15, the cap 113 has a double cylinder form whichincludes a first cap member 113 a fixed to the stem 110 by projectionwelding or the like and a second cap member 113 b fitted into a tip endside of the first cap member 113 a from outward and fixed to the firstcap member 113 a by YAG welding or the like. Specifically, the first capmember 113 a includes stepped outer cylinders, and the outer cylinderhaving a smaller diameter is provided on the tip end of the outercylinder having a larger diameter. An inner cylinder of the one end-sidesecond cap member 113 b is fitted into the outer periphery of the outercylinder having the smaller diameter, and the first cap member 113 a isfixed to the second cap member 113 b by through YAG welding.

On the tip end side of the first cap member 113 a, a lens insertion hole114 is formed and the condenser lens 25 is inserted into this hole 114.The condenser lens 25 is fixed to the first cap member 113 a by a screw,an adhesive material, or the like. An internal space 115 of the firstcap member 113 a is isolated from the outside by a glass window 116,whereby the internal space 115 in which the pedestal 111 is contained iskept airtight. If the internal space 115 can be kept airtight by bondingor soldering the condenser lens 25, the window 116 may be omitted.

In a portion (the other end side) of the second cap member 113 bopposite to the condenser lens 25, a hole 117 for causing the laserlight to pass through is formed. By making an adjustment to positionthis second cap member 113 relative to a laser light axis direction andfixing the second cap member 113 b to the first cap member 113 a by theYAG welding, the condenser lens 25 and a dummy ferrule 118 held in thereceptacle 102 are aligned to each other in the laser light axisdirection.

The receptacle 102 includes a ferrule insertion hole 119 for inserting aferrule 121 (see FIG. 14) to which an optical fiber 120 is connected,and holds the optical fiber 120. The dummy ferrule 118, in which anoptical fiber 118 a is arranged, is press-fitted and fixed into a canpackage 101-side in the ferrule insertion hole 119. One end face of thereceptacle 102 on the side, on which the dummy ferrule 118 is fixed, isfixed to an end face on the other end side of the second cap member 113b is fixed to an end face of the other end side of the second cap member113 b in the can package 101 by butt welding using YAG welding or thelike. By making a positioning adjustment relative to two directionsvertical to the laser light axis direction when fixing the receptacle102 to the second cap member 113 b, the condenser lens 25 is aligned tothe dummy ferrule 118 in the receptacle 102 relative to the twodirections at right angles with respect to the laser light axis.

The ferrule 121 to which the optical fiber 120 is connected, includes anappropriate mechanism (not shown) for pressing the ferrule 121 towardthe dummy ferrule 118 and locking the ferrule 121 to the receptacle 102when the ferrule 121 is inserted into the ferrule insertion hole 119 ofthe receptacle 102. Therefore, if the ferrule 121 is inserted into theferrule insertion hole 119 of the receptacle 102, an end face of theoptical fiber 118 a in the dummy ferrule 118 abuts on an end face of theoptical fiber 120 in the ferrule 121, whereby the fibers are connected(optically coupled) to each other.

The internal configuration of the can package 101 will next beexplained. FIG. 16 is a perspective view which illustrates the canpackage 101 in a state in which the cap 113 is detached.

As shown in FIG. 16, the can package 101 includes the disk-like stem 110on which a plurality of pins are mounted and the trapezoidal pedestal111 vertically fixed to an inner wall surface of the stem 110 by Agbrazing or the like.

On the stem 110 which constitutes a ground, a pair of high frequencysignal pins 141 a and 141 b to which the differential modulated electricsignals (hereinafter, also referred to as “differential high frequencysignals”) are transmitted from the LD driving circuit 1, two ground pins142 a and 142 b arranged on both sides of these high frequency signalpins 141 a and 141 b, one monitor signal pin 143 for transmitting asignal of a monitoring light reception element (e.g., a photodiode,(hereinafter, “PD”)) 150, a pair of bias feed pins 144 a and 144 b forsupplying bias currents from an external DC bias current source to-theLD 20, and a PD chip carrier 145 are mounted. For example, if apositive-phase current signal I₂ shown in FIG. 16 is extracted from thehigh frequency signal pin 141 a, a current I₁ opposite in phase to thecurrent signal I₂ shown in FIG. 16 is applied to the high frequencysignal pin 141 b.

Among these signal pins, the high frequency signal pins 141 a and 141 band the ground pins 142 a and 142 b constitute a feed-through forcausing an electric signal to pass through via the stem 110 while beingkept airtight. The respective pins are fixed to the stem 110 throughdielectrics made of such a material as glass in an airtight sealedstate. The ground pins 142 a and 142 b are fixedly attached to an outerwall surface of the stem 110 that constitutes the ground bypress-fitting or welding. The PD 150 mounted on the PD chip carrier 145is intended to monitor a monitor light emitted from the LD 20 toward abackward direction.

Micro-strip differential line substrates 146 and 147, an LD chip carrier148, and a bias circuit substrate 149 are mounted on an upper surface ofthe pedestal 111. A ground conductor layer that is a plane conductorplate formed on rear surfaces of the micro-strip differential linesubstrates 146 and 147 and the LD chip carrier 148 to function as theground is coupled to the upper surface of the pedestal 111 by solderingor the like and electrically connected thereto. In addition, thepedestal 111 acts as a radiation path for radiating a heat generatedfrom the LD 20 or the like.

The micro-strip differential line substrate 146 includes a ceramicsubstrate 151, a pair of strip differential signal lines 152 a and 152 bformed on an upper surface of the ceramic substrate 151, and the groundconductor layer (not shown) formed on the rear surface of the ceramicsubstrate 151. Pads 153 a and 153 b to contact with the high frequencysignal pins 141 a and 141 b protruding from the stem 110 are formed onone-end sides of the strip differential signal lines 152 a and 152 b,respectively. Capacitive stubs 154 a and 154 a for impedance matchingwhich protrude to be closer to each other signal line are formed halfwayalong the strip differential signal lines 152 a and 152 b, respectively.The strip differential signal lines 152 a and 152 b are set to have alarger distance therebetween in input-side portions near the stem 110 soas to correct an impedance of the field-through section the impedance ofwhich tends to be low. The strip differential signal lines 152 a and 152b each include a portion in which the distance between the signal linesis gradually smaller and an output-side portion in which the distancebetween the signal lines is close and in which the signal lines arearranged in parallel. End portions of the high frequency signal pins 141a and 141 b mounted on the stem 110 are connected and fixed to the pads153 a and 153 b of the micro-strip differential line substrate 146 bybrazing or soldering.

The micro-strip differential line substrate 147 includes a ceramicsubstrate 155, a pair of strip differential signal lines 156 a and 156 bformed on an upper surface of the ceramic substrate 155, and the groundconductor layer (not shown) formed on a rear surface of the ceramicsubstrate 155. Each of the strip differential signal lines 156 a and 156b includes a corner curve portion for turning up a signal line directionby about 90 degrees. The matching resistors 19 a and 19 b for impedancematching are formed halfway along the strip differential signal lines156 a and 156 b, respectively. The strip differential signal lines 152 aand 152 b are connected to the strip differential signal lines 156 a and156 b by wire bonds 157 a and 157 b, respectively.

The LD chip carrier 148 includes micro-strip differential linesincluding a ceramic substrate 158, a pair of strip differential signallines 159 a and 159 b formed on an upper surface of the ceramicsubstrate 158, and the ground conductor layer (not shown) formed on arear surface of the ceramic substrate 158. The LD 20 is mounted on oneend of one strip differential signal line 159 b on the LD chip carrier148 so that the anode that is one of the electrodes of the LD 20directly abuts on one end thereof. The cathode that is the otherelectrode of the LD 20 is connected to one end of the other stripdifferential signal line 159 a by the wire bond 29. The stripdifferential signal lines 156 a and 156 b are connected to the otherends of the strip differential signal lines 159 a and 159 b by wirebonds 161 a and 161 b, respectively. The ceramic substrate 158 is madeof a material having good thermal conductivity such as aluminum nitride(AlN) or silicon carbide (SiC). As the LD 20, a distributed feedbacklaser diode element capable of transmitting a modulated signal at 10Gb/s, for example, is employed.

Two wiring patterns 162 a and 162 b and a pair of inductance circuits(parallel circuits each including the inductance element and theresistor) are formed on the bias circuit (ceramic) substrate 149. Thesolenoid 21 a and the resistor 22 a that prevents a resonance between aninter-line capacitance of the solenoid 21 a and the inductance arearranged to be electrically connected to each other in parallel on theone wiring pattern 162 a. The solenoids 21 a and 21 b are arranged to beaway from each other so that (extension lines of) central axes of thesolenoids 21 a and 21 b cross each other, preferably are orthogonal toeach other to prevent the solenoids 21 a and 21 b from interfering witheach other magnetic field. One end portion of the wiring pattern 162 aand that of the wiring pattern 162 b are connected to the strip linedifferential signal lines 159 a and 159 b through wire bonds 23 a and 23b, respectively. The other end portion of the wiring pattern 162 a andthat of the wiring pattern 162 b are connected to the bias feed pins 144a and 144 b provided on the stem 110 through wire bonds 163 a and 163 b,respectively.

The characteristic configuration of each section in the can package 101will be explained in more detail. The configuration of the stem 110 willfirst be explained.

As shown in FIG. 16, the differential high frequency signals output fromthe differential transistors 12 and 13 in the LD driving circuit 1 areinput to the can package 101 through a grounded coplanar differentialline 170 provided on a substrate arranged outside of the can package101. The grounded coplanar differential line 170 includes a pair ofdifferential signal lines 171 a and 171 b formed on a substrate, grounds172 a and 172 b arranged outside of the differential signal lines 171 aand 171 b to put the paired differential signal lines 171 a and 171 btherebetween, and the ground conductor layer (not shown) arranged on arear surface of the line 170 and connected to the grounds 172 a and 172b. The differential signal lines 171 a and 171 b are connected to outputterminals 160 a and 160 b provided on the upper surface of the LDdriving circuit 1. The output terminal 160 a is electrically connectedto the collector of the differential transistor 13 whereas the outputterminal 160 b is electrically connected to the collector of thedifferential transistor 12.

The differential signal lines 171 a and 171 b of the grounded coplanardifferential line 170 are connected and fixed to the high frequencysignal pins 141 a and 141 b provided on the stem 110 by soldering,respectively. The grounds 172 a and 172 b of the grounded coplanardifferential line 170 are connected and fixed to the ground pins 142 aand 142 b provided on the stem 110 by soldering, respectively. Further,since there is a gap between a can package-side end face of the groundedcoplanar differential line 170 and the stem 110, the reflection of thehigh frequency signals due to the lowering of the impedances may besuppressed by filling this gap with a dielectric.

The stem 110 includes metal such as Kovar (Fe—Ni alloy), soft iron, orCuW (cupper-tungsten), and an upper layer of the stem 110 is normallyplated with Ni, gold or the like for soldering. A plurality of holes174, 175, 176 a, and 176 b are formed to be distributed on the stem 110,and dielectrics 177, 178, 179 a, and 179 b are inserted into therespective holes 174, 175, 176 a, and 176 b.

A pair of pin insertion holes 180 a and 180 b are formed in thedielectric 177, and the high frequency signal pines 141 a and 141 b areinserted into and fixed to the pin insertion holes 180 a and 180 b,respectively. Likewise, holes (reference symbols of which are not shown)are formed in the dielectrics 178, 179 a, and 179 b, and the monitorsignal pin 143 and the bias feed pins 144 a and 144 b are inserted intoand fixed to the holes, respectively. The dielectric 177 into which thepaired high frequency signal pines 141 a and 141 b are inserted has anoval form in this example. Accordingly, the hole 174 into which thedielectric 177 is inserted has an oval form. The other dielectric 178,179 a, and 179 b are circular. It is noted that the ground pins 142 aand 142 b are fixedly attached to an outer wall surface, not shown, ofthe stem 110 by press-fitting and welding.

Lengths of portions of the two high frequency signal pins 141 a and 141b which protrude toward at least one outside of the dielectric 177(protruding lengths toward the LD 20 side) are set smaller than those ofthe monitor signal pin 143 and the bias feed pins 144 a and 144 b inlight of high frequency characteristics. By so setting, the signaltransmitted over the high frequency signal pins 141 a and 141 b can bepromptly transferred to the strip differential signal lines 152 a and152 b on the micro-strip differential line substrate 146 when thesignals are out of the dielectric 177. Since the monitor signal pins 143and the bias feed pins 144 a and 144 b have no strict restrictions forthe high frequency characteristics, the protruding lengths are securedto some extent, thereby facilitating wire bond connection operation andthe like.

As a material for the dielectrics 177, 178, 179 a, and 179 b, Kovarglass, for example, is preferably used or borosilicate glass may beused. As a material for the high frequency signal pins 141 a and 141 b,the monitor signal pin 143, the bias feed pins 144 a and 144 b, and theground pins 142 a and 142 b, metal such as Kovar or 50-percent Ni—Fealloy is used.

The grounded coplanar differential line 170, the high frequency signalpins 141 a and 141 b, the ground pins 142 a and 142 b, the wire bonds157 a and 157 b, and the micro-strip differential line substrates 146and 147 constitute the distributed constant circuit 18.

In the fifth embodiment, in order to make impedance matching from theoutputs of the differential transistors 12 and 13 in the LD drivingcircuit 1 to the LD 20, the paths among them are all constituted by thedifferential lines to drive the LD 20. In addition, as for the pinspenetrating the stem 110, by penetrating the paired high frequencysignal pins 141 a and 141 b through the oval dielectric 177, they act asthe differential pins constituting the differential lines. In, forexample, the single-phase driving type optical semiconductor device,since a high current that drives the LD 20 is fed back to the LD drivingcircuit through the ground, the ground potential changes. This groundpotential change often adversely affects the optical receptionelectronic circuit arranged proximate to the device and detecting thefeeble current. In this embodiment, the optical semiconductor deviceperforms the push-pull operation with respect to the LD 20 using thedifferential lines. Therefore, the optical semiconductor device in thisembodiment has advantages in that the high current is carried across thedifferential lines, the ground potential has less change, and peripheralcircuits are less influenced.

As can be seen, the pin exposure region on the LD driving circuit 1-side is constituted to have the differential lines and the ground pins142 a and 142 b are arranged outside of the region, to thereby set theimpedance of this section lower than that in the conventional opticalsemiconductor device. Therefore, the difference in impedance betweenthis section and the feed-through section is small, as compared with theconventional art and discontinuity of the electric field is reduced, andthe passing characteristics and reflection characteristics can bethereby improved.

The glass is used as the dielectric 177 arranged around the highfrequency signal pins 141 a and 141 b. Therefore, in the inner sectionof the stem (the feed-through section in which the high frequency signalpins 141 a and 141 b are surrounded by the dielectric 177, hereinafter,also referred to as “unexposed region”), if the high frequency signalpins 141 a and 141 b each having a diameter of about 3.5 millimeters to6 millimeters at which the pins can be handled easily are provided, andthe holes of arbitrary shapes are formed in the stem 110 having adiameter of about 3.5 millimeters to 6 millimeters, then the impedanceof the inner section tends to be extremely lowered. To increase theimpedance of this pin unexposed region, a cross-sectional area of thedielectric 177 arranged around the high frequency pins (an area of theoval) may be set large. If so, however, the optical semiconductor devicecannot satisfy requirements for microfabrication and space saving.

Therefore, the protruding lengths of the two high frequency signal pins141 a and 141 b toward the LD 20 are set small so that they can bepromptly transferred to the strip differential signal lines 152 a and152 b on the micro-strip differential line substrate 146 when thesignals are out of the dielectric 177. In addition, the distance betweenthe strip differential signal lines 152 a and 152 b on the micro-stripdifferential line substrate 146 in the portions which are connected tothe high frequency signal pins 141 a and 141 b, respectively and whichare closer to the stem 110 are set larger than the distance therebetweenin, for example, the portions closer to the micro-strip line substrate147, or set slightly larger than the distance between the high frequencysignal pins 141 a and 141 b. By thus setting the distance relativelylarge, the electrical coupling in the portions is made low and theportions are set to have higher impedances.

As can be understood, the distance between the lines in the differentialline portions right after the lines are out of the stem 110 is set largeto thereby purposely create the high impedance portion. The impedance iscancelled by this high impedance portion and the low impedance portioninside of the stem (in the pin unexposed region), whereby impedancematching is made as a whole. In other words, since the pin unexposedregion (feed-through section) is low in impedance, the impedancematching is made in the overall device by slightly generating a highimpedance after the region.

In addition, the paired stubs 154 a and 154 b for impedance matching areformed halfway along the strip differential signal lines 152 a and 152b, respectively. The impedance is reduced by the paired stubs 154 a and154 b, thereby preventing occurrence of mismatching between the stripdifferential signal lines 152 a and 152 b and the strip differentiallines 156 a and 156 b, respectively. In other words, by using the pairedstubs 154 a and 154 b, the reactance components in the driver-side pinexposed region and those in the pin unexposed region (feed-throughsection) are compensated for each other, and the passing characteristicsand the reflection characteristics are thereby improved.

In this case, the paired stubs 154 a and 154 b protrude not outward butinward (so as to be closer to each other signal line), which, therefore,contributes to microfabrication of the micro-strip differential linesubstrate 146. If it is unnecessary to make the micro-strip differentialline substrate 146 small in size, the stubs 154 a and 154 b may protrudeoutward of the differential lines 152 a and 151 b.

In the can package 101, it is necessary to arrange the differential linesubstrates for connecting the high frequency signal pins 141 a and 141 bto the LD 20, the bias circuit substrate for supplying the DC biascurrents to the LD 20, and the monitor PD 50.

If so, the micro-strip differential line substrates 146 and 147 and thebias circuit substrate 149 are arranged on the both sides of the LD chipcarrier 148 to put the LD chip carrier 148 therebetween. In other words,while the LD 20 is put at the center, the strip differential signallines 152 a and 152 b on the micro-strip differential line substrate 146and the strip differential signal lines 156 a and 156 b on themicro-strip differential line substrate 147, the wiring patterns 162 aand 162 b including a pair of inductance circuits, and the LD 20 arearranged generally in a U-shaped fashion.

Furthermore, the micro-strip differential line substrates 146 and 147are provided at the positions shifted sideways from the LD chip carrier148. Naturally, therefore, the transparent dielectric 177 for sealingand fixing the high frequency signal pins 141 a and 141 b is provided atthe position shifted sideways from the LD chip carrier 148.

There is a technique for constituting the substrate on which the LD 20is mounted and the differential line substrates for connecting the highfrequency signal pins 141 a and 141 b to the LD 20 out of the samesubstrate. With this technique, however, a substrate material, such as aaluminum nitride substrate (AlN), expensive per unit area and havinggood radiation characteristics needs to be used in a wide area so as toradiate the heat from the LD 20 that serves as a heat source. Thiscauses a cost hike.

To avoid such a cost hike, the LD chip carrier 148 on which the LD 20serving as the heat source is mounted is separated from the othersubstrates and provided as an independent substrate. Thanks to this, itsuffices to use the ceramic substrate material, such as the aluminumnitride substrate (AlN), which is expensive and which has good radiationcharacteristics only for the LD chip carrier 148 and to use the ceramicsubstrate material, such as inexpensive Al₂O₃ for the other substrates(the micro-strip differential line substrates 146 and 147, and the biascircuit substrate 149). Thus, cost reduction can be realized.

Moreover, according to this embodiment, the micro-strip differentialline substrate 146 for impedance matching and the micro-stripdifferential line substrate 147 for arranging the matching resistors 19a and 19 b are provided as separate substrates. Therefore, it ispossible to cut out the ceramic substrates economically, therebycontributing to cost reduction.

Additionally, the parallel circuit connected to the bias feed pins 144 aand 144 b and including the solenoid 21 a and the resistor 22 a and theparallel circuit including the solenoid 21 b and the resistor 22 b arearranged on the bias circuit substrate 149, thereby reducing the area ofthe bias circuit substrate. This can, therefore, contribute to costreduction and microfabrication.

A thickness of the dielectric 177 is set smaller than a depth of thehole 174 formed in the stem 110, i.e., a width of the stem 110, and ahole 195 having an LD-side opening portion formed conically is formed inthe stem 110.

In this embodiment, the grounded coplanar differential line may beemployed in place of the micro-strip differential line substrates 146and 147. As already explained, the grounded coplanar differential lineincludes the paired differential signal line formed on the substrate,the grounds arranged outside of the differential signal lines so as toput the paired differential signal lines therebetween, and the groundconductor layer arranged on the rear surface of the substrate.

SIXTH EMBODIMENT

The optical semiconductor element module in the sixth embodiment of thepresent invention will be explained with reference to FIG. 17. FIG.17(a) is a top view of the optical semiconductor element module in astate in which an upper cap 401 is detached, and FIG. 17(b) is across-sectional view taken along 11 of FIG. 17(a) (note, however, thatFIG. 17(b) is in a state in which the upper cap 401 is attached).

In this sixth embodiment, the LD 20 mounted on the can package 101explained in the previous embodiment, various constituent elementsincluding a substrate 501 on which the LD 20 is mounted, and the LDdriving circuit 1 are contained in a box-like (butterfly-like) opticalsemiconductor package 402.

As shown in FIG. 17, in this optical semiconductor package 402, thepositive-phase and antiphase differential signals are input to the inputbuffer 11 of the LD driving circuit 1 as already explained. To input thedifferential signals to the LD driving circuit 1 in the opticalsemiconductor package 402, the dielectric 177 (feed-through) is fittedinto a sidewall of the optical semiconductor package 40, and thedifferential signals are transmitted through differential lines 178 aand 178 b provided on the dielectric 177 while keeping an interior andan exterior of the package airtight.

One end of the differential line 1 78 a and that of the differentialline 178 b are soldered to the high frequency signal pins 141 a and 141b, respectively, outside of the optical semiconductor package 402. Thehigh frequency signal pins 141 a and 141 b are arranged proximate toeach other until positions at which the pins 141 a and 141 b are putbetween the ground pins 142 a and 142 b connected to the ground, andconstitute the differential lines.

The other ends of the differential lines 178 a and 178 b are connectedto one ends of differential strip lines 411 provided on a substrate 502,respectively. The other ends of the differential strip lines 411 areconnected to one ends of differential strip lines provided on asubstrate 503. The other ends of the differential strip lines providedon the substrate 503 are connected to differential signal inputterminals of the LD driving circuit 1 through wire bonds, respectively,and electrically connected to the input buffer 11 in the LD drivingcircuit 1.

The output terminals of the LD driving circuit 1 electrically connectedto the differential transistors 12 and 13, are connected to one ends ofthe differential lines provided on a substrate 504 through wire bonds,respectively. The other ends of the differential lines provided on thesubstrate 504 are connected to one ends of differential lines providedon the substrate 501 through wire bonds, respectively. The anode of theLD 20 is soldered to the other end side of one of the differential lineson the substrate 501 as shown in FIG. 5. The other end side of the otherdifferential line on the substrate 501 is connected to the cathode ofthe LD 20 through the wire bond as shown in FIG. 5. The matchingresistors 19 a and 19 b are provided on the one end side of thesubstrate 501. As shown in FIG. 5, the bias circuit 28 a in which thesolenoid 21 a and the resistor 22 a are connected in parallel and thebias circuit 28 b in which the solenoid 21 b and the resistor 22 b areconnected in parallel are provided on the substrate 505. The biascircuits 28 a and 28 b are connected to the differential lines on thesubstrate 501, respectively. Further, the bias circuits 28 a and 28 bare connected to conductor lines on a ceramic substrate 450 through wirebonds, respectively.

The bias circuits 28 a and 28 b are connected to respective conductorleads 451 through wire bonds and the ceramic substrate 450(feed-through). The ceramic substrate 450 is fitted into the sidewall ofthe package, and transmits the bias currents and control signals for theLD driving circuit 1 inside and outside of the optical semiconductorpackage 402 while keeping airtight.

The LD driving circuit 1, and the substrates 501, 503, 504, and 505 aremounted on a metallic conductor mount 510. A lens 520 which includes alens and a holder that holds the lens is coupled to a side surface ofthe metallic conductor mount 510. The lens 520 is arranged to condense alight on the optical fiber 120 through the other optical components.Further, the upper cap 401 is welded to an upper surface of the opticalsemiconductor package 402, and a window glass 600 is coupled to a lightpass-through hole in a front sidewall of the optical semiconductorpackage 402, thereby securing airtightness. The optical fiber 120 isheld by an optical fiber holding section 403.

In this sixth embodiment, the differential signals are input to the LDdriving circuit 1 using the high frequency signal pins 141 a and 141 bconstituting the differential lines, the differential strip lines 411,and the other differential lines. Therefore, similarly to the precedingembodiments, it is possible to suppress the deterioration of the highfrequency characteristics and improve airtightness.

As explained so far, in the optical semiconductor device according tothe present invention, the optical semiconductor element to which thedifferential lines are connected is driven by the push-pull operation.Therefore, the optical semiconductor device has advantages in that theasymmetry of the waveform can be improved, the quality of the opticaloutput waveform can be improved, and that the good transmissioncharacteristics can be thereby obtained.

Moreover, in the optical semiconductor device according to the presentinvention, the bias circuits are arranged on the both electrode sides ofthe optical semiconductor element to which the differential lines areconnected, respectively. Therefore, the optical semiconductor device hasadvantages in that the ripple of the passing characteristics followingthe bias circuits can be improved, the quality of the optical outputwaveform can be improved, and that the good transmission characteristicscan be thereby obtained.

Industrial Applicability

As explained so far, the present invention, as the optical semiconductorelement having good transmission characteristics or as the opticalsemiconductor device that includes the optical semiconductor element, issuited to high speed optical communications.

1. An optical semiconductor device comprising: an optical semiconductorelement; a first conductor line connected to one electrode of a pair ofelectrodes of the optical semiconductor element, and supplying anelectric signal to the optical semiconductor element; a second conductorline connected to the other electrode of the pair of electrodes of theoptical semiconductor element, and supplying an electric signal to theoptical semiconductor element; a first inductance element connected tothe one electrode of the optical semiconductor element and the firstconductor line; and a second inductance element connected to the otherelectrode of the optical semiconductor element and the second conductorline, wherein the first and the second conductor lines constitute a pairof differential lines.
 2. The optical semiconductor device according toclaim 1, further comprising a pair of matching resistors connected tothe one electrode and the other electrode of the optical semiconductorelement, respectively, and introducing the electric signals to theoptical semiconductor element.
 3. The optical semiconductor deviceaccording to claim 2, comprising: a first bias circuit including thefirst inductance element and a first resistor connected in parallel tothe first inductance element; and a second bias circuit including thesecond inductance element and a second resistor connected in parallel tothe second inductance element.
 4. The optical semiconductor deviceaccording to claim 1, comprising: a first bias circuit including thefirst inductance element and a first resistor connected in parallel tothe first inductance element; and a second bias circuit including thesecond inductance element and a second resistor connected in parallel tothe second inductance element.
 5. The optical semiconductor deviceaccording to claim 1, comprising a filter that cuts off frequencieshigher than at least a maximum repetition frequency of a digital signal,the filter provided between the first and the second conductor lines andthe pair of matching resistors.
 6. The optical semiconductor deviceaccording to claim 5, wherein the filter includes a first conductorfinger section and a second conductor finger section in which aplurality of conductors crossing the first and the second conductorlines are formed, respectively, to have a comb shape, the firstconductor finger section and the second conductor finger sections beingalternately arranged.
 7. The optical semiconductor device according toclaim 6, comprising: a package containing therein the first and thesecond conductor lines; a lens that condenses a light emitted from theoptical semiconductor element; and an optical fiber holding member thatholds an optical fiber.
 8. The optical semiconductor device according toclaim 7, wherein the first and the second inductance elements areair-cored coils.
 9. The optical semiconductor device according to claim8, wherein the optical semiconductor element is a semiconductor laserdiode.
 10. The optical semiconductor device according to claim 1,comprising: a package containing therein the first and the secondconductor lines; a lens that condenses a light emitted from the opticalsemiconductor element; and an optical fiber holding member that holds anoptical fiber.
 11. The optical semiconductor device according to claim1, wherein the first and the second inductance elements are air-coredcoils.
 12. The optical semiconductor device according to claim 1,wherein the optical semiconductor element is a semiconductor laserdiode.
 13. The optical semiconductor device according to claim 1,wherein impedances of at least two bias circuits are set asymmetric. 14.An optical semiconductor device comprising: an optical semiconductorelement; a first differential input terminal supplying an electricsignal to one of a pair of electrodes of the optical semiconductorelement; a second differential input terminal supplying an electricsignal opposite in phase to the electric signal supplied by the firstdifferential input terminal, to the other electrode of the pair ofelectrodes of the optical semiconductor element; a first inductanceelement connected to the one electrode of the optical semiconductorelement and the first conductor line, and cutting off the electricsignal at a high frequency; and a second inductance element connected tothe other electrode of the optical semiconductor element and the secondconductor line, and cutting off the electric signal at a high frequency.15. An optical semiconductor device comprising: an optical semiconductorelement; a pair of differential amplifiers each having one terminal andthe other terminal connected to one electrode and the other electrode ofa pair of electrodes of the optical semiconductor element, respectively,and each supplying an electric signal to the optical semiconductorelement; a first inductance element connected to the one electrode ofthe optical semiconductor element, and cutting off the electric signalat a high frequency; and a second inductance element connected to theother electrode of the optical semiconductor element, and cutting offthe electric signal at a high frequency.
 16. An optical semiconductordevice comprising: an optical semiconductor element; first and secondconductor lines connected to a pair of electrodes of the opticalsemiconductor element, and supplying differential signals to the opticalsemiconductor element, respectively; a first terminal electricallyconnected to the first conductor line and one electrode of the pair ofelectrodes of the optical semiconductor element; and a second terminalelectrically connected to the second conductor line and the otherelectrode of the optical semiconductor element, wherein the first andthe second terminals are connected to bias circuits that cut off highfrequencies, respectively.
 17. An optical semiconductor devicecomprising: an optical semiconductor element; a first conductor linehaving one end connected to one of a pair of electrodes of the opticalsemiconductor element, and supplying an electric signal to the opticalsemiconductor element; a second conductor line having one end connectedto the other electrode of the pair of electrodes of the opticalsemiconductor element, and supplying an electric signal to the opticalsemiconductor element; a first inductance element connected to the oneelectrode of the optical semiconductor element and the first conductorline; and a second inductance element connected to the other electrodeof the optical semiconductor element and the second conductor line,wherein the optical semiconductor element is driven by a push-pulloperation.
 18. The optical semiconductor device according to claim 17,wherein impedances of at least two bias circuits are set asymmetric.